1. Field of the Invention
The present invention relates to a semiconductor chip package in which two semiconductor chips are integrated and mounted.
2. Description of the Related Art
Various conventional semiconductor chip packages in which two semiconductor chips are integrated and mounted have been proposed. One example thereof is the BGA (ball grid array) type semiconductor chip package whose cross-sectional structure is illustrated in FIG. 10.
In the case of the semiconductor package structure shown in FIG. 10, electrodes 58 for wiring are aligned on the center of the surface of an upper chip 52. An example of a structure using such an arrangement is a memory LSI. On the other hand, as shown in FIG. 12, electrodes 56 for wiring are aligned in vicinities of each side on the surface of a lower chip 50. An example of a structure using such an arrangement is a logic LSI such as a microcomputer or the like.
The upper chip 52 and the lower chip 50 have been diced and separated into desired sizes. The lower chip 50 is fixed onto a chip mounting position of an interposer 54 formed from a material such as tape or glass epoxy by an adhesive 66 such as an epoxy resin. The upper chip 52 is similarly fixed onto the lower chip 50 by an adhesive 18. FIG. 13 is a schematic plan view showing a state in which the upper and lower chips have been mounted.
Thereafter, the electrodes 58, 56 for wiring of the upper chip 52 and the lower chip 50, respectively, are wire bonded to inner leads 64 on the interposer 54 by wire materials 62, 60 such as metal wires or the like. Then, the structure is resin sealed by a resin sealing material 68 formed from an epoxy resin or the like by a transfer molding method or the like. Finally, solder balls 70 are mounted at outer lead portions of the reverse surface of the interposer, and packaging is completed.
However, this semiconductor chip package, in which two semiconductor chips are integrated and mounted, has the following problems. (1) As can be understood from FIGS. 10 and 13, when the upper chip is integrated on the lower chip, the electrodes for wiring of the lower chip are completely exposed. Further, the present structure cannot be used if the upper chip is not small enough to expose a portion of the surface of the lower chip of a surface area sufficient for carrying out wire bonding by wire materials. (2) The electrodes for wiring can be disposed either in the center of the upper chip or in the vicinities of the respective sides of the upper chip. However, at the lower chip, which must be larger than the upper chip, the electrodes for wiring must be aligned at vicinities of the respective sides, and cannot be aligned in the center. (3) When the electrodes for wiring of the upper chip are aligned in the center of the chip, the wires become long. Thus, problems arise in that there is the concern that short circuits may arise between the wires, and in that the yield is low.